The present invention relates to an electrostatic discharge protection structure.
It is well known that semiconductor Integrated Circuits (IC) may be damaged by Electro-Static Discharge (ESD). Four different causes are identified to be responsible for the ESD phenomenon. The first cause, due to the human-body, results from electrostatic stress exerted on an IC when a human carrying electrostatic charges touches the lead pins of the IC. The second cause, due to handling by a machine, results from electrostatic discharge that occurs when a machine carrying electrostatic charges comes into contact with the lead pins of an IC. The third cause, due to charged devices, results from the ESD current spike generated when an IC lead pins carrying electrostatic charges are grounded during the handling of the IC. The fourth cause, due to induced electric fields, results from the electric field that an IC is exposed to which may produce an ESD in the IC when the IC is later grounded.
Efforts directed at scaling down CMOS processing technologies in order to produce ICs containing transistors with thinner gate oxides and ever decreasing channel dimensions must go hand in hand with development of new structures to protect the ICs against ESD. Therefore, the need continues to exist to reliably protect deep submicron CMOS ICs from the potential damages of ESD.
A well known structure for protecting an IC against ESD damage is a Semiconductor Controlled Rectifier (SCR), also known as a thyristor. FIG. 1A shows a cross-sectional view of a typical lateral SCR 10 which has an anode terminal 12 and a cathode terminal 14. FIG. 1B shows a circuit schematic representation of SCR 10. As is seen from FIG. 1B, SCR 10 is composed of an npn bipolar transistor 32, a pnp bipolar transistor 30 and two parasitic resistors 34 and 36. In order to turn on SCR 10, a positive voltage must be applied between anode terminal 12 and cathode terminal 14 to forward bias both transistors 30 and 32. When SCR 10 turns on, a low impedance discharge path forms between the two terminals of SCR 10 to discharge the current.
FIG. 1C shows the current-voltage characteristic of SCR 10. In FIG. 1C, the vertical axis represents the current flow between terminals 12 and 14, and the horizontal axis represents the voltage across terminals 12 and 14 of SCR 10. The voltage at which SCR 10 enters the region characterized by a negative current-voltage relationship is called the snap-back or the trigger voltage, which is shown in FIG. 1C as Vt.
A major disadvantage of SCR 10 is that it provides protection against ESD in only one direction, i.e. either against a positive voltage/current pulse or against a negative voltage/current pulse. Consequently, to protect an IC against ESD, one SCR must be disposed between each input/output pad of the IC and the positive supply voltage and one SCR must be disposed between each input/output pad and the negative supply voltage. Alternatively, an IC is protected against ESD damage by a SCR which provides an active discharge path in one supply direction (positive or negative) and which provides a discharge path through parasitic diodes in the other supply direction. Therefore, what is needed is a single ESD protection structure capable of protecting an IC against both positive and negatives ESD pulses.
FIG. 1D shows a top view of SCR 10 constructed using conventional layout techniques. The rectangular shape of p+ region 20 or n+ region 22 is known in the art as a finger structure. When an ESD pulse appears across anode terminal 12 and cathode terminal 14, current enters into or departs from p+ region 20 and n+ regions 22 from across only a single edge of each of the fingers, designated in FIG. 1D with solid arrows 30. In order to increase the current handling capabilityxe2x80x94hence to improve the ESD performance of SCR 10xe2x80x94prior art layout techniques add more n+ fingers in p-type substrate 24 and more p+ fingers in n-well 26. However, by thus adding more p+ and n+ fingers, a significant amount of semiconductor surface area is occupied without a proportional increase in the ESD performance of the resulting structure. This is because, the current flow between each pair of newly added p+ and n+ fingers is limited to a component crossing only a single edge of each of the added fingers. It is, therefore, advantageous to develop an ESD layout structure which provides for current flow across more edges of the p+ and n+ finger.
Referring to FIG. 1A, the trigger voltage, Vt, of SCR 10 depends on the concentration profile of the impurities that form the n-type and the p-type semiconductor regions of SCR 10. Therefore, once SCR 10 is fabricated using a conventional IC fabrication process technology, its trigger voltage cannot be changed.
Often an IC includes several subcircuits which operate at different supply voltages. For example, some blocks of circuitry within an IC may require five volts to operate, while other blocks of circuitry within the same IC may require fifteen volts to operate. Because SCR 10 has a fixed trigger voltage, it is not suitable for use as an ESD protection device in a multi-supply voltage IC. To protect a multi-supply voltage IC against ESD, prior art techniques use different ESD protection structures that trigger at different voltages. It is, therefore, advantageous to have a single ESD structure whose trigger voltage is varied to accommodate for ESD protection at different supply voltages.
An Electro-Static Discharge (ESD) protection structure, in accordance with the present invention, protects an Integrated Circuit (IC) against both positive and negative ESD pulses.
The ESD protection structure has an anode terminal and a cathode terminal and is composed of five semiconductor regions to form an n-p-n-p-n device. The ESD structure, hence, includes one pnp bipolar transistor, two npn bipolar transistors and four parasitic resistors.
When the voltage potential of an ESD pulse appearing across the two terminals of the ESD protection structure exceeds the reverse breakdown voltage of the collector-base junction of the pnp transistor, electron-hole pairs are generated. The holes thus generated flow toward the cathode terminal, forcing the npn transistor whose emitter region is connected to the cathode terminal to turn on. Subsequently, the ESD protection structure enters into a snap-back mode, thereby, to form a low impedance current discharge path between the two terminals to discharge the ESD current. The trigger voltage of the ESD protection structure of the present invention is hence determined by the reverse-breakdown voltage of the collector-base junction of the pnp transistor.
Some embodiments of the ESD protection structure of the present invention are formed by combining a number of standard cells, in accordance with the present invention. The standard cells which include a center cell, an edge cell and a corner cell are arranged adjacent each other in a particular fashion to form a square-shaped n-p-n-p-n ESD protection structure which provides a low impedance current discharge path from many locations therein. Accordingly, the square-shaped ESD protection structure thus formed has an enhanced current handling capability. Advantageously, the number of standard cells used to construct a square-shaped ESD protection structure may be varied at will to increase or decrease the amount of the current that is discharged.
Some embodiments of the present invention have a variable trigger voltage. To achieve trigger voltage variability, the base terminal of each of the npn transistors is coupled to a network consisting of a pair of back-to-back zener diodes connected in series with a resistor. Depending on the polarity of the applied ESD pulse, one of the zener diode pairs turns on thereby to generate current to the resistor connected thereto. The voltage developed across the resistor raises the base-emitter voltage of the npn transistor coupled thereto, thereby triggering the ESD protection structure.